1. Field of the Invention
The present invention relates generally to semiconductor wafer preparation systems and method for preparing wafers, more particularly, the present invention relates to the cleaning and drying of semiconductor wafers using space and process efficient systems.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform chemical mechanical polishing (CMP) operations and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material grows. Without planarization, fabrication of further metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns (e.g., copper metal) are formed in the dielectric material, and then, metal CMP operations are performed to remove excess metallization. After any such CMP operation, it is necessary that the planarized wafer be cleaned to remove particulates and contaminants.
In the prior art, wafer cleaning systems typically implement brush stations in which polyvinyl alcohol (PVA) brushes are used to scrub both sides of a wafer. The PVA brush material is configured to be soft enough to prevent damage to the wafer""s delicate surface, yet can provide good mechanical contact with the wafer surface to dislodge residues, chemicals and particulates. Each of the brushes are typically configured to deliver chemicals and or DI water through the brush (TTB). Commonly, two brush stations are used, each with a pair of brushes, to enable the application of chemicals in one brush station and DI water in the other. This dual brush station approach has been shown to improve the cleaning performance as well as increase throughput. One physical layout of the cleaning system is to arrange the brush stations longitudinally (i.e., horizontally). The wafer therefore travels from one brush station to the next along a conveying system. Once the wafer has been processed in both brush stations, the wafer is then conveyed to a next station in which the wafer is subjected to a spin, rinse, and dry (SRD) operation, which is performed in an SRD station or dryer station. Because these stations are arranged horizontally, the machine necessarily occupies a large clean room footprint, in some systems being as long as 6-7 feet by 3 feet wide.
In other wafer cleaning systems, such as the one described in U.S. Pat. No. 5,875,507, which is herein incorporated by reference, the illustrated wafer cleaning systems and a dryer system are also arranged horizontally. An end effector robot is configured to handle the wafers and transport them between each cleaning station and the dryer system. This arrangement, although efficient in cleaning wafers in vertical orientations, takes up substantial clean room area. Additionally, this arrangement requires that the robot handle the wafer at each stage of the process. That is, the robot is required to bring wafers into and out of each cleaning station and also into and out of the dryer. This level of interaction, although configured to be as clean as possible, can introduce particulates and can slow down the process.
In view of the foregoing, there is a need for wafer preparation systems that are more compact, occupy smaller clean room footprints, and shelter a wafer from excessive transport operations between preparation operations (e.g., such as cleaning, etching, drying and the like).
Broadly speaking, the present invention fills these needs by providing a wafer preparation system incorporating a scrubber and a dryer that are vertically oriented and configured to accomplish essential wafer processing while minimizing system footprint, minimizing wafer transport operations, and thereby minimizing auxiliary systems such as robots for end effectors. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a wafer preparation system is disclosed. The wafer preparation system includes a scrubber unit that is configured to receive a wafer for mechanical scrub cleaning. A dryer unit is located above the scrubber unit in a vertical orientation. The dryer unit is configured to receive the wafer from the scrubber unit after the mechanical scrub cleaning, and then dry the wafer.
In another embodiment, a method of wafer preparation is disclosed. The wafer preparation method includes receiving a wafer in a scrubbing station. The method further provides the lifting of the wafer from the scrubbing station to a drying station that is arranged vertically over the scrubbing station.
In yet another embodiment, a wafer scrubbing and drying apparatus is disclosed. The wafer scrubbing and drying apparatus includes a scrubber unit that has scrub brushes oriented to scrub a wafer in a vertical orientation. A dryer unit is positioned over a top region of the scrubber unit, and the dryer unit is configured to receive the wafer from the scrubber unit. The wafer is received in a vertical orientation by the dryer from a slot in the top region of the scrubber unit.
In still a further embodiment, a semiconductor wafer preparation apparatus is disclosed. The semiconductor wafer preparation apparatus includes a wafer cleaning station and a drying station that is mounted over the wafer cleaning station.
The advantages of the present invention are many and substantial. Most notably, the vertical orientation of the wafer preparation system significantly reduces system footprint and required clean room floor space. The vertical orientation represents a significant advancement over prior art that extends preparation systems over a large floor space area and requires repeated robot wafer handling to transport wafers from one preparation station or unit to the next. The present invention not only minimizes required floor space, but minimizes the need for repeated robot handling, reducing both the cost of operation and the potential for contamination.
Another advantage of the present invention is the embodiment that provides increased flexibility in wafer preparation processes by accommodating both chemical cleans or etching processes and DI water rinses in both scrubber and dryer units. The vertical orientation of the wafer preparation system incorporates a dual brush set in the scrubber unit which can dispense both chemicals and DI water in whatever combination the wafer process dictates. The dryer unit is also configured to dispense both chemicals and DI water, and in the vertical orientation, the wafer preparation system can incorporate an environment that gets progressively cleaner as the wafer proceeds higher in the system. Thus, the first scrub operation can be the most vigorous and successive etch, clean and rinse operations can be in cleaner conditions, the successive operations being located higher in the vertically oriented system.
Finally, a preferred embodiment of the present invention affords a more efficient process with increased throughput over prior art. A single robot can load wafers into the scrubber unit of the wafer preparation system and unload wafers from the dryer unit. In a vertical orientation, multiple wafer preparation systems can be implemented to share resources in smaller floor space areas to maximize the savings and efficiency achieved.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.